The present invention relates in general to phase lock loops and, more particularly, to charge pump bias control in a phase lock loop.
Phase lock loops (PLLs) are widely used for frequency synthesis. A conventional PLL may include a phase detector for monitoring a phase difference between an input signal and an output signal of a current controlled oscillator (ICO). The phase detector generates an up control signal and a down control signal for a charge pump to source and sink current through a low-pass loop filter to the input of the ICO. The positive and negative current pulses flowing from the charge pump into the ICO determine its output frequency. The up and down control signals driving the charge pump set the proper current levels into the ICO to maintain a predetermined phase relationship between the signals applied to the phase detector.
In the PLL frequency synthesizer application, a first programmable frequency divider is typically placed in the input signal path while a second programmable frequency divider is located between the output of the ICO and the second input of the phase detector. The output frequency of the PLL is given by input signal frequency times the ratio of the second frequency divider to the first frequency divider.
The PLL often includes both analog and digital processing. The phase detector and programmable frequency dividers are typically digital while the charge pump, low-pass loop filter and ICO operate analog. The lock status of the PLL is discretely sampled at the active edges of the input signals to the phase detector. The sampling rate is determined by the input signal frequency divided by the first programmable frequency divider. In order to suppress the noise in the system, the PLL bandwidth needs to be as large as possible. However, to maintain stable operation, the unity gain bandwidth of the PLL must be much less than digital sampling frequency. To properly control the sample rate, prior art PLL synthesizers have employed digital-to-analog converters (DAC) controlled by the first and second frequency divider ratios to perform the necessary tracking. Unfortunately, the use of DACs increase the chip area and cost of manufacturing and contribute to system noise.
Hence, a need exists for a PLL frequency synthesizer operating with a unity gain bandwidth smaller than the digital sampling frequency by a constant factor.